1. Field of the Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to a diagonal matrix delay for delaying an input signal.
2. Background Information
FIG. 1 is a circuit diagram illustrating a conventional matrix delay 100 for delaying an input signal 103 and providing an output signal 107. For purposes of illustration, the delay matrix 100 can be comprised of eight rows (i.e., Row 0, Row 1, . . . , Row 7), with each row comprised of eight delay elements 105. The rows are arranged in serial communication with each other, with the delay elements 105 within each row serially coupled to provide incremental delays for the input signal 103. The output of each delay element 105 in each row is in communication with a buffer 110, such as a tri-state buffer. The buffers 110 associated with each row are arranged in (vertical) columns. For purposes of illustration, the buffers 110 associated with each row are arranged in eight columns (i.e., Column 0, Column 1, . . . , Column 7) to receive the output of each delay element 105.
The buffers 110 associated with each column are configured to receive a control signal for selecting a vertical column of buffers 110. For example, control line 130 is coupled to each of the buffers 110 vertically associated with Column 0 to receive control signal 120, control line 131 is coupled to each of the buffers 110 vertically associated with Column 1 to receive control signal 121, and so forth. The outputs of the buffers 110 associated with each row are coupled together to form an output for the row that is applied to a corresponding row selection buffer 115 (e.g., a tri-state buffer). A row selection signal 140–147 is applied to a row selection buffer 115 to select the output for a particular row.
To select a delay for the input signal 103 using the matrix delay 100, one of the eight columns of buffers 110 is selected by applying a control signal 120–127 to the control line 130–137 associated with the appropriate vertical column. In addition, one of the eight rows is selected by applying a row selection signal 140–147 to the row selection buffer 115 associated with the appropriate row. For example, the delay provided by matrix delay 100 can be incremented or decremented by a single delay element 105 at a time. However, with the conventional matrix delay 100, if a move to the next row is necessary to increment the delay by one (i.e., the buffer 110 associated with the last column—Column 7—of the present row is currently selected), the buffer 110 associated with the first (vertical) column (i.e., Column 0) of the next row must be selected. In addition, within a row, only moves between buffers 110 in contiguous columns can be made at any one time (e.g., from Column 1 to Column 2, not from Column 1 to Column 3), when the delay is changed by a single delay element 105 at a time. Thus, if Row n and Column 7 is currently selected, to move to Row n+1, the row selection signal for Row n is changed to “disabled,” the row selection signal for Row n+1 is changed to “enabled,” the control signal 127 for Column 7 is changed to “disabled,” and the control signal 120 for Column 0 is changed to “enabled.” Consequently, when moving from the last column of a row to the first column of the next row to increase the delay by a single delay element 105, at least four selectors must be changed for the delay matrix 100. Four selectors must also be changed when moving from the first column of a row to the last column of the previous row to decrease the delay by a single delay element 105.
However, to make the changes between rows in the matrix delay 100, all changes must be made simultaneously with a “zero” transition. If not made simultaneously, the output 107 can have an unknown state, since two (tri-state) buffers can be open and two (tri-state) buffers can be closed when the row is changed. In addition, if the changes are not made with a “zero” transition, a spike or other electrical disturbance can be created on the output 107.